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Abstraction Levels

Designs are so complex and time-to-market so short that developers can no longer use low-level representations (e.g. RTL for hardware, assembly for software) to develop systems. Higher abstraction levels are required when developing systems in order to master complexity and reduce development times.
Co-design involves jointly developing the hardware and software parts of a system. Thus, software needs to be developed and validated before the final hardware is available.
 
During the functional and architectural design steps, developers create a virtual architecture of the system. It represents an abstraction of the final system and provides developers with means to validate the entire system through co-simulation. At this stage, it is essential to define the right abstraction level since it impacts simulation time and effectiveness. A low-level simulation such as RTL simulation or ISS is very precise but very slow. Verifying very complex system requires 100 to 1000x faster simulation speed so it can be used in an interactive development process. However, a description at a higher abstraction level has to be precise enough to represent accurate real-time system behavior and to generate code for prototyping or implementation/synthesis purposes.
 
Any kind of model always describes 3 types of views on a system: structural/organizational, behavioral and communications. There are typically 5 common levels of abstraction for all models: service, message, transaction, transfer and register transfer (or logic/gate).*
The most significant view for characterizing an abstraction level is the communications one. To each abstraction level corresponds a model for communications defined by its time accuracy/dependency and types of media, addressing, data and protocol.

Abstraction levelsCharacteristics of communications model
ParadigmMediaAddressingProtocolDataReal-time behavior
Service
(e.g. CORBA)
Un-timed functionalAbstract networkAutomaticService request: do somethingAbstractUnpredictable (service/ request causality)
Message
(e.g. MCSE, SDL, UML)
(Un-) Timed functionalLogical network of active channelsAbstract & explicitHigh-level primitives:
send/receive
AbstractPossibly predictable
(ordering of messages)
Transaction
(e.g. CSP, SystemC, Cossap)
Bus cycle-accurateLogical linksLogical & explicitRead/write data
Wait for new event
Varying sizeSynchronized to bus cycle
Transfer
(e.g. VHDL, Verilog)
Cycle-accurateLogical linksLogical & explicitRead/write data
Wait for new clock cycle
Fixed sizeSynchronized to clock cycle
Register transfer
(e.g. VHDL, Verilog)
Pin-accuratePhysical linksPhysical & explicitSet/reset ports
Wait for new clock cycle
Bit/ data on busSynchronized to clock cycle
Communications abstraction levels

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Virtual architecture and prototype creation process
 
Simulation speed and behavioral real-time accuracy depends on the abstraction levels at which communications and computation (as part of the behavioral view) are described. They also largely impact the complexity of the simulation environment and the exploitability of results obtained. Service- and message-level models can be simulated on the development host platform using a native technology such as SystemC, while lower-level models require dedicated target hardware. Of course, RTL and transaction-level simulation technologies (respectively ISS and ISA) are closer to a real-world execution than higher level models, but significant results can be difficult to obtain and exploit.
 
CoFluent Studio creates different models at the message level. Models are precise enough and fully timed to simulate accurately the system’s real-time behavior. They are at a high-enough level of abstraction to enable high-speed hardware/software co-simulation (about 1000x RTL simulation speed). In addition, they provide developers with high-level simulation results for early and easy co-verification, avoiding any paradigm shift from modeling to verification.
 
CoFluent Studio’s flexible architecture modeling capabilities enable designers to easily explore multiple architectural choices.
Furthermore, models are precise enough to deliver accurate performances data (with an estimated error margin around 5%) during simulation. Performances analysis is based on simple configuration parameters describing the macroscopic properties of the system’s architectural components. It does not require separate simulation or special system editing.
 
Last, the description of the system’s behavior is detailed enough to generate a virtual prototype of the system that can be later used for software implementation and hardware simulation/synthesis.



*Abstraction levels definition and table courtesy of Jean Paul Calvez and Gabriela Nicolescu, excerpt from chapter 2 Spécification et modélisation des systèmes embarqués of the book edited by A. A. Jerraya and G. Nicolescu: La spécification et la validation des systèmes hétérogènes embarqués (publisher: Hermes, Collection "Techniques de l'ingénieur").


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