CoFluent exhibits at DAC 2010
Date: May 12, 2010
CoFluent Design exhibits at the 47th Design Automation Conference taking place in Anaheim, California, on June 13-18, 2010.
DAC is the world's leading technical conference and tradeshow, covering the latest trends in electronic design and design automation. DAC is where the IC Design and EDA ecosystem learns, networks, and does business - where critical industry issues are faced and solutions presented.
Come to visit us at our booth # 1415 to get a demo of the latest CoFluent products.
Check out CoFluent Design's Virtual DAC booth
Demos at DAC
- Docea Power Aceplorer interoperability demo
This demonstration shows that a power use case (or power scenario), which is a description of power state changes for different components and other information, can be generated from a CoFluent Studio architectural model simulation. This scenario is generated in VCD format to be opened in Docea Aceplorer tool for early detailed power and thermal exploration.
- Mentor Graphics Questa interoperability demo
We demonstrate how to reuse on Questa a message-level SystemC HW IP model that is generated automatically by CoFluent Studio. The CoFluent IP serves as a golden reference to validate the behavior of a cycle-accurate bit-true RTL IP. The CoFluent IP and the RTL IP are stimulated with the same cycle-accurate bit-true signals that are sent by a SystemVerilog testbench. A simple wrapper is added around the CoFluent IP to convert cycle-accurate bit-true signals to message-level transactions, and vice versa.
- Synopsys Innovator interoperability demo
This demonstration shows how to quickly create workload models for verifying a TLM 2.0-based virtual platform. Dynamic use cases are graphically captured, timings and algorithms are incorporated and CoFluent Studio automatically generates the corresponding SystemC model that can be imported into Synopsys Innovator or CoWare Platform Architect. The demo example is based on AT communications between a traffic generator sending read and write requests to a memory through an interconnect.
- UML/SysML modeling and simulation demo
This demonstration shows how to use SysML and the UML MARTE profile to model an embedded application and use cases within MagicDraw, and execute the models within CoFluent Studio.
- Architecture exploration demo
This demonstration shows how to model and simulate an embedded application and use cases running on a multiprocessor hardware platform for behavior, real-time, performance and power prediction.
- Embedded C/POSIX code generation demo
This demonstration is based on a v3.2.1 pre-release integrating the MDWorkbench runtime used for generating text from CoFluent models. The code generation allows to automatically translate a CoFluent application model into a multithread embedded real-time application software written in C for the POSIX API. The obtained C code can be built and run on a Linux machine used for the demo.
- Word doc generation demo
This demonstration is based on a v3.2.1 pre-release integrating the MDWorkbench runtime used for generating text from CoFluent models. The doc generation allows to automatically create a Word project document including all model information based on a user-customizable template.
CoFluent Design is part of the IC Design Central (ICDC) Partner Pavilion
The IC Design Central Partner Pavilion illustrates the many critical design functions necessary to produce working silicon, on time and on budget. Besides EDA vendors, companies from all areas of the design and product development process. DAC has created the IC Design Central Partner Pavilion to help DAC attendees find the exact design flows and solutions they need to create today's challenging designs.
- IC DESIGN CENTRAL Presentation from CoFluent Design
CoFluent Design: Multicore System Modeling and SystemC-Based Simulation with UML, SysML and MARTE
Topic Area: System-Level and Embedded
Wednesday, June 16, 2010
Time: 12:30 PM - 1:00 PM
Location: Exhibit Hall B - Booth #1710
Summary:CoFluent Design introduces a new UML methodology for modeling and simulating embedded systems and chips. It combines SysML and MARTE profiles, and is supported by the CoFluent Studio software based on Eclipse. CoFluent Studio allows designers to model real-time applications and use cases, and simulate their execution on multiprocessor/multicore platforms. Simulation allows for behavioral and real-time validation, as well as performance and power prediction. SystemC TLM code is automatically generated from UML models, and can be reused as functional or test case model in verification and virtual platform environments from CoWare, Synopsys and Mentor Graphics.
CoFluent Design on Synopsys Standards Booth
As System-Level Catalyst Program member, CoFluent Design participates at the Synopsys Standards Booth.
CoFluent Design will give a presentation and demonstration of CoFluent Studio integration to Innovator and Platform Architect at the system-level pod on Monday, June 14 from 2:00 to 4:00 PM.